1. Field of the Invention
The present invention relates to a method of manufacturing an alignment mark of a semiconductor device, and more particularly, to a method of manufacturing an alignment mark which is used in an alignment between plural layer patterns when a multitiered structure semiconductor device is formed.
The present application claims priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2001-159214, filed May 28, 2001, which is herein incorporated by reference in its entirely for all purposes.
2. Description of the Related Art
A conventional method of manufacturing an alignment mark is disclosed in, for example, Japanese Laid-Open Patent Publication: HEI06-021406, published on Jan. 28, 1994.
FIG. 7 is a flow chart showing a conventional process for manufacturing an alignment mark, in the case of a silicon-on-insulator (SOI) semiconductor structure.
First, as shown in a step 701, an SOI substrate is formed. The representative methods of manufacturing the SOI substrate are bonding technology methods and oxide ion implantation methods. In bonding technology, a silicon wafer having an oxide layer is bonded to another silicon wafer which does not have an oxide film. On the other hand, in oxide ion implantation, an oxide ion is implanted into a silicon wafer, and then a high-temperature thermal treatment is performed.
Next, as shown in step 702, a photolithography using an alignment for an element isolation pattern is performed, and a resist pattern having openings is generated. The openings of the resist pattern are located at alignment mark regions and vernier regions. Next, as shown in a step 703, a silicon etching is performed to remove the SOI layer (the silicon layer) of the SOI wafer at locations of the alignment mark regions and the vernier regions, using a second resist pattern as a mask. Next, as shown in a step 704, a resist peeling is performed to remove the second resist.
Then, a positioning is performed using the alignment mark formed as above, and the positioning is confirmed using the vernier.
More specifically, the following process steps are usually used for an SOI structure wafer (an SOI wafer) having the element isolation pattern.
(1) A forming step of the element isolation pattern. (Isolation regions are formed.)
(2) A forming step of the bond SOI wafer. (Bonding and polishing are performed.)
(3) A forming step of the semiconductor device.
An input into the step (3) after a termination of the step (2) is referred to a line re-input. The SOI layer located at the alignment regions and the vernier regions of the SOI wafer having the element isolation pattern are etched during the line re-input. As a result, sufficient level differences of these regions are ensured. The SOI layer at other regions (e.g. an element formation region) is masked by the resist pattern, and are not etched. Therefore, a photolithography step of aligning the lower element isolation pattern is required. At this time, it is possible to sufficiently detect a signal waveform indicative of the alignment mark for following reasons:
(1) A top layer of the alignment mark and vernier regions is different from that of the element isolation region. The top layer of the alignment mark and vernier regions is consisted of a silicon oxide (SiO2), on the other hand, the top layer of the element isolation region is a silicon (Si).
(2) A range of tolerance with respect to deviation in the alignment is large. At this time, a fine alignment of 0.15 xcexcm is not required, and about 2.0 xcexcm is sufficient.
As a result, a clear signal waveform indicative of the alignment mark is obtained. Specifically, since a sufficient level difference of the alignment mark region can be secured, a signal waveform having a sufficient S/N ratio can be obtained.
The alignment mark which is used to the manufacturing process of the semiconductor device having such an SOI structure, is formed by removing the SOI layer of the alignment mark region by etching. However, a thickness of the SOI layer is gradually being reduced to achieve certain technical device advantages (e.g. high integration, high functionality, low power supply voltage, etc.). Therefore, differences in the alignment mark region decrease more and more. As a result, a signal waveform having a sufficient S/N ratio can not be obtained, and it becomes difficult to accurately detect such an alignment mark.
According to one aspect of the present invention, in a method of manufacturing an alignment mark, a silicon-on-insulator (SOI) substrate is provided having a grid-line region and a circuit region, and including a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, an element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate, the insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.
According to the present invention, since the alignment mark is constructed with a deep concave portion, the alignment mark can be detected with a high degree of accuracy in various alignment steps.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and accompanying drawings.